Profiling floating point value ranges for reconfigurable implementation

نویسندگان

  • Ashley W Brown
  • Paul H J Kelly
  • Wayne Luk
چکیده

Reconfigurable architectures offer potential for performance enhancement by specializing the implementation of floating-point arithmetic. This paper presents FloatWatch, a dynamic execution profiling tool designed to identify where an application can benefit from reduced precision or reduced range in floating-point computations. FloatWatch operates on x86 binaries, and generates a profile output file recording, for each instruction and line of source code, the overall range of floating-point values, the bucketised sub-ranges of values, and the maximum difference between 64-bit and 32-bit executions. We present results from the tool on a suite of four benchmark codes. Our tool indicates potential performance loss due to denormal values, and helps to identify opportunities for using dual fixed-point arithmetic representation which has proved effective for reconfigurable designs. Our results show that applications often have highly modal value distributions, offering promise for aggressive floating-point arithmetic optimisations.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Welcome to the First HiPEAC Workshop on Reconfigurable Computing

Reconfigurable architectures offer potential for performance enhancement by specializing the implementation of floating-point arithmetic. This paper presents FloatWatch, a dynamic execution profiling tool designed to identify where an application can benefit from reduced precision or reduced range in floating-point computations. FloatWatch operates on x86 binaries, and generates a profile outpu...

متن کامل

Profile-directed speculative optimization of reconfigurable floating point data paths

This paper presents a methodology for generating floatingpoint arithmetic hardware designs which are, for suitable applications, dramatically reduced in size, while still retaining performance. We use a profiling tool for floating-point value ranges to identify arithmetic operations where the shifting required for alignment and normalisation is almost always small. We synthesise hardware with r...

متن کامل

Customising Floating-Point Designs

This paper describes a method for customising the representation of floating-point numbers that exploits the flexibility of reconfigurable hardware. The method determines the appropriate size of mantissa and exponent for each operation in a design, so that a cost function with a given error specification for the output relative to a reference representation can be satisfied. Currently our tool,...

متن کامل

Block Floating Point Implementations for DSP Computations in Reconfigurable Computing

The IEEE-754 standard prescribes standards for 32 bit single precision and 64 bit double precision formats. For DSP applications that require a large dynamic range floating point implementations are more suitable than fixed point representation. This advantage is offset by the cost of the implementation. The block floating point (BFP) concept combines the precision and cost effectiveness of fix...

متن کامل

Speculative Reduction of Floating Point Datapaths

This paper presents a methodology for generating floatingpoint arithmetic hardware designs which are, for suitable applications, dramatically reduced in size, while still retaining performance. We use a profiling tool for floating-point value ranges to identify arithmetic operations where the shifting required for operand alignment is almost always small. We synthesise hardware with reduced-siz...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2006